HT1627
RAM Mapping 6416 LCD Controller for I/O mC
Selection Table
HT162X
HT1620 HT1621 HT1622 HT16220 HT1623 HT1625 HT1626 HT1627 HT16270
COM
4
4
8
8
8
8
16
16
16
SEG
32
32
32
32
48
64
48
64
64
Built-in Osc.
Crystal Osc.
1
April 21, 2000
Features
Operating voltage: 2.7V~5.2V
Built-in RC oscillator
1/5 bias, 1/16 duty, frame frequency is 64Hz
Max. 6416 patterns, 16 commons,
64 segments
Built-in internal resistor type bias generator
3-wire serial interface
8 kinds of time base /WDT selection
Time base or WDT overflow output
Built-in LCD display RAM
R/W address auto increment
Two selection buzzer frequencies
(2kHz/4kHz)
Power down command reduces power
consumption
Software configuration feature
Data mode and Command mode instructions
Three data accessing modes
VLCD pin to adjust LCD operating voltage
Cascade application
General Description
HT1627 is a peripheral device specially de-
signed for I/O type mC used to expand the dis-
play capability. The max. display segment of
the device are 1024 patterns (6416). It also
supports serial interface, buzzer sound, Watch-
dog Timer or time base timer functions. The
HT1627 is a memory mapping and multi-func-
tion LCD controller. The software configuration
feature of the HT1627 make it suitable for mul-
tiple LCD applications including LCD modules
and display subsystems. Only three lines are
required for the interface between the host con-
troller and the HT1627. The HT162X series
have many kinds of products that match vari-
ous applications.
Block Diagram
Pin Assignment
HT1627
2
April 21, 2000
SE
G
2
SE
G
0
SE
G
1
SE
G
3
SE
G
6
H T 1 6 2 7
1 0 0 Q F P
3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0
8 1
8 2
8 3
8 4
8 5
8 6
8 7
8 8
8 9
9 0
9 1
9 2
9 3
9 4
9 5
9 6
9 7
9 8
9 9
1 0 0
8 0
7 9
7 8
7 7
7 6
7 5
7 4
7 3
7 2
7 1
7 0
6 9
6 8
6 7
6 6
6 5
6 4
6 3
6 2
6 1
6 0
5 9
5 8
5 7
5 6
5 5
5 4
5 3
5 2
5 1
SE
G
4
SE
G
5
SE
G
7
SE
G
8
SE
G
9
SE
G
1
0
SE
G
1
1
SE
G
1
2
SE
G
1
3
SE
G
1
4
SE
G
1
5
SE
G
1
6
SE
G
4
8
SE
G
5
6
SE
G
5
5
SE
G
5
4
SE
G
5
3
SE
G
5
2
SE
G
5
1
SE
G
5
0
SE
G
4
9
SE
G
5
7
SE
G
4
7
SE
G
4
6
SE
G
4
5
SE
G
4
4
SE
G
6
1
SE
G
6
0
SE
G
5
9
SE
G
5
8
CO
M
1
3
CO
M
1
4
CO
M
1
5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
SE
G
6
3
SE
G
6
2
S E G 1 7
S E G 1 8
N C
N C
S E G 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
S E G 2 9
S E G 3 0
S E G 3 1
S E G 3 2
S E G 3 3
S E G 3 4
S E G 3 5
S E G 3 6
S E G 3 7
S E G 3 8
S E G 3 9
S E G 4 0
S E G 4 1
N C
S E G 4 2
S E G 4 3
V S S
D A T A
W R
R D
C S
O S C I
V D D
V L C D
I R Q
B Z
B Z
T 3
T 2
T 4
T 1
C O M 0
C O M 1
C O M 2
C O M 3
C O M 4
C O M 5
C O M 6
C O M 7
C O M 8
C O M 9
C O M 1 0
C O M 1 1
C O M 1 2
N C
N C
W a t c h d o g T i m e r
a n d
T i m e B a s e G e n e r a t o r
D i s p l a y R A M
L C D D r i v e r /
B i a s C i r c u i t
C o n t r o l
a n d
T i m i n g
C i r c u i t
D A T A
W R
O S C I
C S
R D
C O M 0
C O M 1 5
S E G 0
S E G 6 3
T o n e F r e q u e n c y
G e n e r a t o r
B Z
B Z
I R Q
V S S
V D D
V L C D
Pad Assignment
Chip size: 245 237 (mil)
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
HT1627
3
April 21, 2000
I R Q
B Z
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2 2 3
2 4 2 5
2 6 2 7
2 8 2 9
3 0 3 1
3 2 3 3
3 4 3 5
3 6 3 7
3 8 3 9
4 0 4 1
4 2 4 3
4 4 4 5
4 6 4 7
4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
5 7
5 8
5 9
6 0
6 1
6 2
6 3
6 4
6 5
6 6
6 7
6 8
6 9
7 0
7 1
7 2
7 3
7 4
7 5
7 6
7 7
7 8
7 9
8 0
8 1
8 2
8 3
8 4
8 5
8 6
8 7
8 8
8 9
9 0
9 1
9 2
9 3
9 4
9 5
( 0 , 0 )
D A T A
V S S
O S C I
V D D
V L C D
B Z
T 1
T 2
T 3
T 4
C O M 0
C O M 1
C O M 2
C O M 3
C O M 4
C O M 6
C O M 5
C O M 8
C O M 7
C O M 9
CO
M
1
1
CO
M
1
0
CO
M
1
2
CO
M
1
4
CO
M
1
3
CO
M
1
5
SE
G
0
SE
G
1
SE
G
2
SE
G
3
SE
G
4
SE
G
5
SE
G
6
SE
G
7
SE
G
8
SE
G
9
SE
G
1
0
SE
G
1
1
SE
G
1
2
SE
G
1
3
SE
G
1
4
SE
G
1
5
SE
G
1
6
SE
G
1
7
S E G 1 8
S E G 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
S E G 2 9
S E G 3 0
S E G 3 1
S E G 3 2
S E G 3 3
S E G 3 4
S E G 3 5
S E G 3 6
S E G 3 7
S E G 3 8
S E G 3 9
S E G 4 0
S E G 4 1
SE
G
4
2
SE
G
4
4
SE
G
4
3
SE
G
4
6
SE
G
4
5
SE
G
4
8
SE
G
4
7
SE
G
5
0
SE
G
4
9
SE
G
5
2
SE
G
5
1
SE
G
5
4
SE
G
5
3
SE
G
5
6
SE
G
5
5
SE
G
5
8
SE
G
5
7
SE
G
6
0
SE
G
5
9
SE
G
6
2
SE
G
6
1
CS
SE
G
6
3
WR
RD
Pad Coordinates
Unit: mil
Pad No.
X
Y
Pad No.
X
Y
Pad No.
X
Y
1
-116.62
99.88
33
-14.96
-112.03
65
116.15
55.72
2
-116.71
86.32
34
-2.97
-112.03
66
116.15
67.70
3
-116.71
78.75
35
3.65
-112.03
67
116.15
74.33
4
-116.71
72.12
36
15.64
-112.03
68
116.15
86.32
5
-115.94
65.49
37
22.27
-112.03
69
116.15
92.95
6
-116.71
55.97
38
34.26
-112.03
70
116.15
104.93
7
-116.71
41.44
39
40.88
-112.03
71
112.03
112.24
8
-116.71
21.84
40
52.87
-112.03
72
100.04
112.24
9
-115.94
11.39
41
59.50
-112.03
73
93.42
112.24
10
-115.94
-0.60
42
71.49
-112.03
74
81.43
112.24
11
-115.94
-7.22
43
78.11
-112.03
75
74.80
112.24
12
-115.94
-19.21
44
90.10
-112.03
76
62.81
112.24
13
-115.94
-25.84
45
96.73
-112.03
77
56.19
112.24
14
-115.94
-37.83
46
108.71
-112.03
78
44.20
112.24
15
-115.94
-44.46
47
116.15
-111.82
79
37.57
112.24
16
-115.94
-56.44
48
116.15
9.83
80
25.58
112.24
17
-115.94
-63.07
49
116.15
-93.20
81
18.95
112.24
18
-115.94
-75.06
50
116.15
-81.22
82
6.97
112.24
19
-115.94
-81.68
51
116.15
-74.59
83
0.34
112.24
20
-115.94
-93.67
52
116.15
-62.60
84
-11.65
112.24
21
-115.94
-100.30
53
116.15
-55.97
85
-18.27
112.24
22
-115.94
-112.29
54
116.15
-43.99
86
-30.26
112.24
23
-108.04
-112.03
55
116.15
-37.36
87
-36.89
112.24
24
-96.05
-112.03
56
116.15
-25.37
88
-48.88
112.24
25
-89.42
-112.03
57
116.15
-18.74
89
-55.51
112.24
26
-77.43
-112.03
58
116.15
-6.76
90
-67.49
112.24
27
-70.81
-112.03
59
116.15
-0.13
91
-74.12
112.24
28
-58.82
-112.03
60
116.15
11.86
92
-86.11
112.24
29
-52.19
-112.03
61
116.15
18.49
93
-92.74
112.24
30
-40.21
-112.03
62
116.15
30.47
94
-104.72
112.24
31
-33.58
-112.03
63
116.15
37.10
95
-114.24
112.24
32
-21.59
-112.03
64
116.15
49.09
HT1627
4
April 21, 2000
Pad Description
Pad No.
Pad Name
I/O
Description
1
DATA
I/O Serial data input/output with pull-high resistor
2
VSS
Negative power supply, Ground
3
OSCI
I
If the system clock comes from an external clock source, the ex-
ternal clock source should be connected to the OSCI pad.
4
VDD
Positive power supply
5
VLCD
I
LCD operating voltage input pad.
6
IRQ
O Time base or Watchdog Timer overflow flag, NMOS open drain
output
7, 8
BZ, BZ
O 2kHz or 4kHz tone frequency output pair (Tri-state output
buffer)
9~12
T1~T4
I
Not connected
13~28
COM0~COM15 O LCD common outputs
29~92
SEG0~SEG63
O LCD segment outputs
93
CS
I
Chip selection input with pull-high resistor. When the CS is
logic high, the data and command read from or write to the
HT1627 are disabled. The serial interface circuit is also reset.
But if the CS is at logic low level and is input to the CS pad, the
data and command transmission between the host controller
and the HT1627 are all enabled.
94
RD
I
READ clock input with pull-high resistor. Data in the RAM of
the HT1627 are clocked out on the rising edge of the RD signal.
The clocked out data will appear on the data line. The host con-
troller can use the next falling edge to latch the clocked out data.
95
WR
I
WRITE clock input with pull-high resistor. Data on the DATA
line are latched into the HT1627 on the rising edge of the WR
signal.
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V
Storage Temperature.................-50C to 125C
Input Voltage................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature ..............-25C to 75C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maxi-
mum Ratings may cause substantial damage to the device. Functional operation of this de-
vice at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
HT1627
5
April 21, 2000
D.C. Characteristics
Ta=25C
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
V
DD
Conditions
V
DD
Operating Voltage
2.7
5.2
V
I
DD1
Operating Current
3V No load/LCD ON
On-chip RC oscillator
200
315
mA
5V
300
425
mA
I
DD2
Operating Current
3V No load/LCD OFF
On-chip RC oscillator
15
55
mA
5V
30
85
mA
I
STB
Standby Current
3V No load
Power down mode
2
14
mA
5V
4
28
mA
V
IL
Input Low Voltage
3V
DATA, WR, CS, RD
0
0.6
V
5V
0
1.0
V
V
IH
Input High Voltage
3V
DATA, WR, CS, RD
2.4
3
V
5V
4.0
5
V
I
OL1
BZ, BZ, IRQ
3V V
OL
=0.3V
0.9
1.8
mA
5V V
OL
=0.5V
1.7
3
mA
I
OH1
BZ, BZ
3V V
OH
=2.7V
-0.9 -1.8
mA
5V V
OH
=4.5V
-1.7
-3
mA
I
OL2
DATA
3V V
OL
=0.3V
0.9
1.8
mA
5V V
OL
=0.5V
1.7
3
mA
I
OH2
DATA
3V V
OH
=2.7V
-0.9 -1.8
mA
5V V
OH
=4.5V
-1.7
-3
mA
I
OL3
LCD Common Sink Current
3V V
OL
=0.3V
80
160
mA
5V V
OL
=0.5V
180
360
mA
I
OH3
LCD Common Source Current
3V V
OH
=2.7V
-40
-80
mA
5V V
OH
=4.5V
-90 -180
mA
I
OL4
LCD Segment Sink Current
3V V
OL
=0.3V
50
100
mA
5V V
OL
=0.5V
120
240
mA
I
OH4
LCD Segment Source Current
3V V
OH
=2.7V
-30
-60
mA
5V V
OH
=4.5V
-70 -140
mA
R
PH
Pull-high Resistor
3V
DATA, WR, CS, RD
100
200
300
kW
5V
50
100
150
kW
HT1627
6
April 21, 2000
A.C. Characteristics
Ta=25C
Symbol
Parameter
Test Conditions
Min. Typ. Max. Unit
V
DD
Conditions
f
SYS1
System Clock
3V On-chip RC oscillator
22
32
40
kHz
5V
24
32
40
kHz
f
SYS2
System Clock
3V
External clock source
32
kHz
5V
32
kHz
f
LCD1
LCD Frame Frequency
3V
On-chip RC oscillator
44
64
80
Hz
5V
48
64
80
Hz
f
LCD2
LCD Frame Frequency
3V
External clock source
64
Hz
5V
64
Hz
t
COM
LCD Common Period
n: Number of COM
n/f
LCD
sec
f
CLK1
Serial Data Clock (WR Pin)
3V
Duty cycle 50%
150
kHz
5V
300
kHz
f
CLK2
Serial Data Clock (RD Pin)
3V
Duty cycle 50%
75
kHz
5V
150
kHz
t
CS
Serial Interface Reset Pulse
Width
(Figure 3) CS
250
ns
t
CLK
WR, RD Input Pulse Width
(Figure 1)
3V
Write mode
3.34
ms
Read mode
6.67
5V
Write mode
1.67
ms
Read mode
3.34
t
r
, t
f
Rise/Fall Time Serial Data
Clock Width
(Figure 1)
3V
120
ns
5V
t
su
Setup Time for DATA to WR,
RD Clock Width (Figure 2)
3V
120
ns
5V
t
h
Hold Time for DATA to WR,
RD Clock Width (Figure 2)
3V
120
ns
5V
t
su1
Setup Time for CS to WR,
RD Clock Width (Figure 3)
3V
100
ns
5V
t
h1
Hold Time for CS to WR, RD
Clock Width
(Figure 3)
3V
100
ns
5V
HT1627
7
April 21, 2000
HT1627
8
April 21, 2000
9 0 %
5 0 %
1 0 %
G N D
W R , R D
C l o c k
t
f
t
r
t
C L K
t
C L K
V
D D
Figure 1
5 0 %
V A L I D D A T A
5 0 %
D B
W R , R D
C l o c k
G N D
t
s u
t
h
V
D D
V
D D
G N D
Figure 2
S E G 0
S E G 1
S E G 2
S E G 3
S E G 6 3
C O M 1 2
C O M 1 3
C O M 1 4
C O M 1 5
A d d r
2 5 5
3
7
1 1
1 5
C O M 0
C O M 1
C O M 2
C O M 3
A d d r
2 5 2
0
4
1 2
8
D a t a 4 B i t s
( D 3 , D 2 , D 1 , D 0 )
A d d r e s s 8 B i t s
( A 7 , A 6 , . . . . , A 0 )
D 3
D 2
D 1
D 0
D a t a
D 3
D 2
D 1
D 0
D a t a
RAM mapping
Functional Description
Display memory - RAM structure
The static display RAM is organized into 256*4
bits and stores the display data. The contents of
the RAM are directly mapped to the contents of
the LCD driver. Data in the RAM can be ac-
cessed by the READ, WRITE and READ-MOD-
IFY-WRITE commands. The following is a map-
ping from the RAM to the LCD patterns.
Time base and Watchdog Timer - WDT
The time base generator and WDT share the
same divided (/256) counter. TIMER DIS/EN/CLR
, WDT DIS/EN/CLR and IRQ EN/DIS are inde-
pendent from each other. Once the WDT
time-out occurs, the IRQ pin will remain at
logic low level until the CLR WDT or the IRQ
DIS command is issued.
C S
G N D
5 0 %
5 0 %
F I R S T
C l o c k
L A S T
C l o c k
G N D
W R , R D
C l o c k
t
s u 1
t
h 1
t
C S
V
D D
V
D D
Figure 3
HT1627
9
April 21, 2000
W D T E N / D I S
I R Q E N / D I S
D
C K
Q
R
C L R W D T
C l o c k S o u r c e
/ 4
/ 2 5 6
T i m e B a s e
C L R T i m e r
I R Q
W D T
V
D D
T I M E R E N / D I S
Timer and WDT configurations
If an external clock is selected as the source of
system frequency, the SYS DIS command turns
out invalid and the power down mode fails to be
carried out until the external clock source is re-
moved.
Buzzer tone output
A simple tone generator is implemented in the
HT1627. The tone generator can output a pair
of differential driving signals on the BZ and BZ
which are used to generate a single tone.
Command format
The HT1627 can be configured by the software
setting. There are two mode commands to con-
figure the HT1627 resource and to transfer the
LCD display data.
The following are the data mode ID and the
command mode ID:
Operation
Mode
ID
READ
Data
1 1 0
WRITE
Data
1 0 1
READ-MODIFY-WRITE
Data
1 0 1
COMMAND
Command 1 0 0
If successive commands have been issued, the
command mode ID can be omitted. While the
system is operating in the non-successive com-
mand or the non-successive address data mode,
the CS pin should be set to 1 and the previous
operation mode will be reset also. The CS pin
returns to 0, a new operation mode ID should
be issued first.
Name
Command Code
Function
TONE OFF
0000-1000-X
Turn-off tone output
TONE 4K
010X-XXXX-X
Turn-on tone output, tone frequency is 4kHz
TONE 2K
0110-XXXX-X
Turn-on tone output, tone frequency is 2kHz
Timing Diagrams
READ mode (command code : 1 1 0)
READ mode (successive address reading)
HT1627
10
April 21, 2000
R D
D A T A
W R
1
1
0
A 7
A 6
A 1
A 0
D 0 D 1
D 2
D 3
M e m o r y A d d r e s s 1 ( M A 1 )
D a t a ( M A 2 )
1
1
0
A 1
A 0
D 0 D 1
D 2
D 3
D a t a ( M A 1 )
M e m o r y A d d r e s s 2 ( M A 2 )
A 7
A 6
A 5
A 4
A 3
A 2
A 5
A 4
A 3
A 2
C S
R D
D A T A
C S
W R
1
1
0
A 1
A 0
D 0 D 1
D 2
D 3
M e m o r y A d d r e s s ( M A )
D a t a ( M A )
D 0 D 1
D 2
D 3
D 0 D 1
D 2
D 3
D 0 D 1
D 2
D 3
D 0
D a t a ( M A + 1 )
D a t a ( M A + 2 )
D a t a ( M A + 3 )
A 7
A 6
A 5
A 4
A 3
A 2
WRITE mode (command code : 1 0 1)
WRITE mode (successive address writing)
HT1627
11
April 21, 2000
D A T A
C S
W R
1
0
1
A 7
A 6
A 1
A 0
D 0 D 1
D 2
D 3
M e m o r y A d d r e s s 1 ( M A 1 )
D a t a ( M A 1 )
1
0
1
A 1
A 0
D 0 D 1
D 2
D 3
M e m o r y A d d r e s s 2 ( M A 2 )
D a t a ( M A 2 )
A 7
A 6
A 5
A 4
A 3
A 2
A 5
A 4
A 3
A 2
D A T A
C S
W R
1
0
1
A 1
A 0
D 0 D 1
D 2
D 3
M e m o r y A d d r e s s ( M A )
D a t a ( M A )
D 0 D 1
D 2
D 3
D 0 D 1
D 2
D 3
D 0 D 1
D 2
D 3
D 0
D a t a ( M A + 1 )
D a t a ( M A + 2 )
D a t a ( M A + 3 )
A 7
A 6
A 5
A 4
A 3
A 2
READ-MODIFY-WRITE mode (command code ; 1 0 1)
READ-MODIFY-WRITE mode (successive address accessing)
HT1627
12
April 21, 2000
D A T A
C S
W R
1
0
1
A 6
A 7
A 1
A 0
D 0 D 1
D 2
D 3
M e m o r y A d d r e s s 1 ( M A 1 )
D a t a ( M A 1 )
A 1
A 0
D 0 D 1
D 2
D 3
M e m o r y A d d r e s s 2 ( M A 2 )
D a t a ( M A 2 )
1
0
1
R D
D 0 D 1
D 2
D 3
D a t a ( M A 1 )
A 6
A 7
A 4
A 5
A 2
A 3
D A T A
C S
W R
1
0
1
A 1
A 0
D 0 D 1
D 2
D 3
M e m o r y A d d r e s s ( M A )
D a t a ( M A )
D 0 D 1
D 2
D 3
D 0 D 1
D 2
D 3
D 0 D 1
D 2
D 3
D 0
D a t a ( M A )
D a t a ( M A + 1 )
D a t a ( M A + 1 )
R D
D 1
D 2
D 3
D 0
D a t a ( M A + 2 )
A 6
A 7
A 4
A 5
A 2
A 3
Command mode (command code : 1 0 0)
Mode (data and command mode)
HT1627
13
April 21, 2000
D A T A
C S
W R
1
0
0
C 8
C 7
C 6
C 5
C 4
C 3 C 2 C 1
C 0
C o m m a n d 1
C 8
C 7
C 6
C 5
C 4
C 3 C 2 C 1
C 0
C o m m a n d i
C o m m a n d . . .
C o m m a n d
o r
D a t a M o d e
R D
D A T A
C S
W R
A d d r e s s a n d D a t a
C o m m a n d
o r
D a t a M o d e
A d d r e s s a n d D a t a
C o m m a n d
o r
D a t a M o d e
A d d r e s s a n d D a t a
C o m m a n d
o r
D a t a M o d e
Application Circuits
*Note: The connection of IRQ and RD pin can be selected depending on the requirement of the mC.
The voltage applied to V
LCD
pin must be lower than V
DD
.
Adjust VR to fit LCD display, at V
DD
=5V, V
LCD
=4V, VR=15kW20%.
Adjust R (external pull-high resistance) to fit users time base clock.
HT1627
14
April 21, 2000
B Z
I R Q
H T 1 6 2 7
D A T A
1 / 5 B i a s , 1 / 1 6 D u t y
C S
R D
W R
m C
L C D P a n e l
C O M 0 ~ C O M 1 5
S E G 0 ~ S E G 6 3
B Z
*
R*
P i e z o
V R
*
V D D
V L C D
Instruction Set Summary
Name
ID
Command Code
D/C
Function
Def.
READ
1 1 0 A7A6A5A4A3A2A1A0D0D1D2D3 D Read data from the RAM
WRITE
1 0 1 A7A6A5A4A3A2A1A0D0D1D2D3
D Write data to the RAM
READ-
MODIFY-
WRITE
1 0 1 A7A6A5A4A3A2A1A0D0D1D2D3
D Read and Write data to the RAM
SYS DIS
1 0 0 0000-0000-X
C Turn off both system oscillator
and LCD bias generator
Yes
SYS EN
1 0 0 0000-0001-X
C Turn on system oscillator
LCD OFF
1 0 0 0000-0010-X
C Turn off LCD display
Yes
LCD ON
1 0 0 0000-0011-X
C Turn on LCD display
TIMER DIS 1 0 0 0000-0100-X
C Disable time base output
Yes
WDT DIS
1 0 0 0000-0101-X
C Disable WDT time-out flag output Yes
TIMER EN
1 0 0 0000-0110-X
C Enable time base output
WDT EN
1 0 0 0000-0111-X
C Enable WDT time-out flag output
TONE OFF 1 0 0 0000-1000-X
C Turn off tone outputs
Yes
CLR TIMER 1 0 0 0000-1101-X
C Clear the contents of the time base
generator
CLR WDT
1 0 0 0000-1111-X
C Clear the contents of the WDT stage
RC 32K
1 0 0 0001-10XX-X
C System clock source, on-chip RC
oscillator
Yes
EXT 32K
1 0 0 0001-11XX-X
C System clock source, external clock
source
TONE 4K
1 0 0 010X-XXXX-X
C Tone frequency output: 4kHz
TONE 2K
1 0 0 0110-XXXX-X
C Tone frequency output: 2kHz
IRQ DIS
1 0 0 100X-0XXX-X
C Disable IRQ output
Yes
IRQ EN
1 0 0 100X-1XXX-X
C Enable IRQ output
F1
1 0 0 101X-0000-X
C Time base clock output: 1Hz
The WDT time-out flag after: 4s
F2
1 0 0 101X-0001-X
C Time base clock output: 2Hz
The WDT time-out flag after: 2s
F4
1 0 0 101X-0010-X
C Time base clock output: 4Hz
The WDT time-out flag after: 1s
HT1627
15
April 21, 2000
Name
ID
Command Code
D/C
Function
Def.
F8
1 0 0 101X-0011-X
C Time base clock output: 8Hz
The WDT time-out flag after: 1/2 s
F16
1 0 0 101X-0100-X
C Time base clock output: 16Hz
The WDT time-out flag after: 1/4 s
F32
1 0 0 101X-0101-X
C Time base clock output: 32Hz
The WDT time-out flag after: 1/8 s
F64
1 0 0 101X-0110-X
C Time base clock output: 64Hz
The WDT time-out flag after: 1/16 s
F128
1 0 0 101X-0111-X
C Time base clock output: 128Hz
The WDT time-out flag after: 1/32 s Yes
TEST
1 0 0 1110-0000-X
C Test mode, user dont use.
NORMAL
1 0 0 1110-0011-X
C Normal mode
Yes
Note: X : Dont care
A7~A0 : RAM address
D3~D0 : RAM data
D/C : Data/Command mode
Def. : Power on reset default
All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates
the command mode ID. If successive commands have been issued, the command mode ID ex-
cept for the first command will be omitted. The source of the tone frequency and of the time
base/WDT clock frequency can be derived from an on-chip 32kHz RC oscillator or an external
32kHz clock. Calculation of the frequency is based on the system frequency sources as stated
above. It is recommended that the host controller should initialize the HT1627 after power on
reset, for power on reset may fail, which in turn leads to the malfunctioning of the HT1627.
HT1627
16
April 21, 2000
HT1627
17
April 21, 2000
Copyright 2000 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may pres-
ent a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
PDF 
ZIP